Metal gate technology allows for improved MOSFET device performance over conventional semiconductor MOSFET devices using semiconductor gate electrodes, due to elimination of the depletion layer in the gate; thus, decreasing the electrical inversion oxide thickness, tinv, by about 3–5 Å without incurring a subsequent significant increase in gate oxide leakage current. Typically, semiconductor gate electrodes are formed from polysilicon (poly or poly-Si, amorphous Si, SiGe etc.). MOSFET devices with fully silicided gate electrodes (FUSI gates) allow for thinner electrical inversion oxide thickness, tinv resulting in improved device performance due to increased carrier density in the channel, and also improved control over short-channel effects. Recently, it has been shown that pre-doping of a polysilicon gate electrode along with a high temperature anneal to drive the dopant atoms to the dielectric interface, prior to the silicidation reaction will adjust the workfunction of the resulting metal electrode. As a result, reducing the threshold voltage via compensating channel implant is not required and surface-channel MOSFET operation can be achieved. Specifically, polysilicon gates pre-doped with Antimony (Sb), a well-known n-type dopant, at high doses approaching 4×1015 cm−3 similar to a standard polysilicon gate pre-doping step, then properly annealed at high temperatures, and finally fully silicided using Ni as the starting material, has a workfunction shift compared to an undoped NiSi gate from mid-gap to roughly 120 meV from the conduction band edge. On the other hand, a p-type dopant has yet to be found that can significantly shift the workfunction towards the valence band edge; thus the technique of pre-doping fully silicided gates is less effective for pFET devices. Using current methods, in order to obtain a workfunction that is within 200 meV from the valence band edge, a different metal silicide material, for example, using a NiPt alloy with a 30% Pt concentration, may be required. The use of different processes for silicidation of the nFET and pFET gate conductors makes integration of both nFET and pFET devices difficult, especially in tightly packed memory cells. Hereinafter, for convenience, the use of the term silicidation is meant to include any process of forming a semiconductor metal alloy, the term silicide is meant to include any such resulting semiconductor metal alloy and the term silicided is meant to include any appropriate semiconductor that has been converted to a semiconductor metal alloy, and is not meant to be limited to processes or materials involving only silicon semiconductors.
Accordingly, it would be desirable to provide a structure and method for cost effective integration of fully silicided (FUSI) MOSFET devices in dense layouts that takes advantage of improved performance of FUSI gates without a significant adverse impact on the electrical properties of the MOSFETs.